Many integrated circuits include a package, such as a ball grid array, to provide an electrical interface between the integrated circuits and other external electronics, such as a circuit board. Unlike integrated circuit packages that provide connections along the perimeter of the package, such as dual-in-line (DIP), small outline IC (SOIC), or plastic leaded chip carrier (PLCC), ball grid arrays provide a high signal count in a small area to reduce the size of a packaged device and the board area consumed when mounted to a circuit board. A typical ball grid array can include multiple solder balls or bumps arranged in an orthogonal row-column format, with solder balls in a common row or a common column having a preset pitch or spacing between each other. The pitch or spacing between the solder balls can be utilized for routing traces from the solder balls to interface pads of the integrated circuits or to other devices on the circuit board.
For standard ball grid array packages, a number of solder balls in the ball grid array can be modified in order to accommodate modification in a number of signals entering or exiting the integrated circuits. As a number of solder balls increases, the ball grid array packages can increase in size or a pitch between the solder balls can be reduced. An increase in package size can increase cost, while the reduction in the pitch between the solder balls can be rendered impossible or impractical by introducing difficulties in the routing of traces or coupling the integrated circuit package to the circuit board.
A specialized form of a ball grid array, called a wafer-level chip scale package (WLCSP), can use a semiconductor die, for example, made of silicon or other semiconductor base material, such as sapphire, silicon carbide, gallium arsenide, as a package substrate to provide a small mounted footprint. Modifications to a size of the WLCSP, for example, increasing a package size to accommodate additional signals, directly corresponds to an increase in the semiconductor die size itself, which can work against a goal of reducing a mounted footprint.
The semiconductor die for WLCSP packaged devices often can be difficult or not economical to produce in form factors matching those of standard packages or ball grid spacings. Specific structures, such as the repeated cell dimensions of static random access memories (SRAMs), flash memories, dynamic random access memories (DRAMs), etc, are often highly asymmetrical when replicated millions of times on a device. As such, placement of a grid of orthogonally spaced solder balls may become difficult to impossible given the constraints of signal count and ball pitch. Also, in devices where it was originally possible to place a standard orthogonal grid, an optical shrink of a masking process, often used to improve manufacturing efficiencies of semiconductors, may yield a new die where a standard grid may no longer be usable.